This invention relates to a current memory cell for applying to a current terminal, during a hold interval, an output current which is substantially equal to an input current forced onto the current terminal during a sample interval preceding the hold interval, comprising:
a first current terminal, PA1 a first transistor having a source, a drain and a gate, the drain being coupled to the first current terminal, PA1 a capacitor inserted between the source and gate of the first transistor, and PA1 a first switch for coupling the gate of the first transistor to the first current terminal during the sample interval. PA1 a second current terminal, PA1 second and third transistors of a conductivity type opposite to that of the first transistor and each having a source, drain and gate, the drain of the second transistor being coupled to the first current terminal and the drain of the third transistor to the second current terminal, the gate of the second transistor being connected to the gate of the third transistor and gate-source junctions formed by the gates and sources of the second and third transistors being connected in parallel, and PA1 a second switch for coupling the gates of the second and third transistors to the first current terminal during the hold interval and to the second current terminal during the sample interval. PA1 a second current terminal PA1 second and third transistors of a conductivity type opposite to that of the first transistor and each having a source, drain and gate, the drain of the second transistor being coupled to the first current terminal and the drain of the third transistor to the second current terminal, the gate of the second transistor being connected to the gate of the third transistor and gate-source junctions formed by the gates and sources of the second and third transistors being connected in parallel, PA1 means for producing a substantially constant voltage difference between the gate of the third transistor and the second current terminal, and PA1 a bias current source which is coupled to the second current terminal. PA1 a further bias current source, PA1 a cascode transistor and a negative feedback transistor both of the same conductivity type as that of the associated first, second and third transistors, and having a source, drain and gate, the drain of the cascode transistor being connected to the associated current terminal, the source of the cascode transistor and the gate of the negative feedback transistor being connected to the drains of the associated first, second and third transistors, the source of the negative feedback transistor being coupled to the sources of the associated first, second and third transistors and the drain of the negative feedback transistor and the gate of the cascode transistor being connected to the bias current source.
A current memory cell of this type is known from U.S. Pat. No. 4,967,140. Current memory cells of this prior-art type are used as a current source that can be calibrated in accurate digital-to-analog converters, as a current memory in analog discrete-time signal processing (switched current technique), dynamic current mirror circuits and current dividers. They are also termed current copiers.
The first transistor of the current memory cell is often an NMOS transistor in a P-type substrate of an integrated circuit. Owing to the body effect the current memory cell is sensitive to substrate voltage variations caused by, for example, a digital circuit realised on the same substrate. During the hold interval the gate of the NMOS transistor has a tri-state, the voltage on the capacitor built up by the forced current during the sample interval insures that the supplied current is maintained. Voltage variations between the source and the substrate may then affect the supplied current as a result of the body effect. The effect may be reduced by locally connecting the substrate to the source. However, this has only a partial effect because the substrate underneath the gate cannot be reached directly. Furthermore, for different reasons it is often undesired to connect the source of the current memory cell to the substrate. The NMOS current memory cell is also sensitive to minority carriers which are generated by a noise source located on the same chip and are captured by the NMOS transistor.
For specific applications it is possible to use PMOS current memory cells in lieu of NMOS current memory cells, the PMOS transistor being embedded in an N-well which may be connected to any desired noise-free voltage. This solution is only possible if the direction of the forced input current and the supplied output current in a system does not play any part. However, there are also systems in which the use of both types of current memory cells is necessary, such as two-way digital-to-analog converters. One type of current memory cell (NMOS) then operates as a current sink and the other type of current memory cell (PMOS) as a current source.